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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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MC33121 Low Voltage Subscriber Loop Interface Circuit (SLIC) Thin Film Silicon Monolithic Integrated Circuit
The MC33121 is designed to provide the interface between the 4-wire side of a central office, or PBX, and the 2-wire subscriber line. Interface functions include battery feed, proper loop termination AC impedance, hookswitch detection, adjustable transmit, receive, and transhybrid gains, and single/ double fault indication. Additionally, the MC33121 provides a minimum of 58 dB of longitudinal balance (4-wire and 2-wire). The transmit and receive signals are referenced to analog ground, while digital signals are referenced to digital ground, easing the interface to codecs, filters, etc. The 2 status outputs (hookswitch and faults) and the Power Down Input are TTL/CMOS compatible. The Power Down Input permits local shutdown of the circuit. Internal drivers allow the external loop current pass transistors to be standard bipolar transistors (non-Darlington). The MC33121 is available in a 20 pin DIP and a 28 pin PLCC surface mount package. * * * * * * * * * * * 58 dB Longitudinal Balance Guaranteed; 4-wire and 2-wire Transmit, Receive, and Transhybrid Gains Externally Adjustable Return Loss Externally Adjustable Proper Hookswitch Detection With 30 k Leakage Single/Double Fault Indication With Shutdown for Thermal Protection Critical Sense Resistors Included Internally Standard Power Supplies: - 21.6 V to - 42 V, and + 5.0 V, 10% On-Hook Transmission Power Down Input (TTL and CMOS Compatible) Operating Ambient Temperature: - 40C to + 85C Available in a 20 Pin DIP and 28 Pin PLCC Package SIMPLIFIED BLOCK DIAGRAM
VCC EP BP TIP CP VEE TSI RSI VCC RING CN BN EN - + - + VDD (+5.0 V) VDG (DIG. GND) PDI/ST2 ST1
20 1
P SUFFIX PLASTIC PACKAGE CASE 738
28
FN SUFFIX PLCC CASE 776
1
ORDERING INFORMATION
Device MC33121P MC33121FN Temperature Range - 40 to + 85C Package Plastic DIP PLCC
*
CURRENT MIRROR
CURRENT MIRROR
CURRENT MIRROR
*
HOOK STATUS AND FAULT DETECTION AND BIAS CONTROL BIAS + -
+ -
VAG (ANA. GND) RXI TXO RFO CF VQB
*
CURRENT MIRROR CURRENT MIRROR CURRENT MIRROR
VEE (BATTERY)
*
MC33121
* Indicates trimmed resistor
REV 1.0 4/96
(c) Motorola, Inc. 1996 MOTOROLA
MC33121 1
MAXIMUM RATINGS
Characteristic Supply Voltage (with respect to VCC) (with respect to VDG) Voltage @ PDI, (with respect to VDG) @ CP, CN EP, TSI BP RSI, EN BN Junction Temperature Storage Temperature Symbol VEE VDD Vin - 0.5, + 7.0 VEE - 0.5, VCC + 0.5 VCC - 7.0, VCC + 0.5 VCC - 14, VCC + 0.5 VEE - 0.5, VCC + 14 VEE - 1.0, VEE + 21 TJ Tstg 150 - 65 to + 150 C C Value - 60, + 0.5 - 0.5, + 7.0 Vdc Unit Vdc
* Devices should not be operated at these limits. The "Recommended Operating Conditions" table provides for actual device operation.
RECOMMENDED OPERATING CONDITIONS
Characteristic Supply Voltage (with respect to VCC) (with respect to VDG) (with respect to VCC) (with respect to VCC) (with respect to VAG) (with respect to VEE) (with respect to VCC and VAG) Loop Current PDI Input Voltage Sink Current ST1 ST2 Transmit Signal Level at Tip & Ring Receive Signal Level at VRX Loop Resistance VEE = - 42 V VEE = - 24 V Symbol VEE VDD VAG VDG VDD IL VPDI IST1L IST2L STX SRX RL Hfe TA Min - 42 + 4.5 - 3.0 - 3.0 - 3.0 -- 3.5 15 0 0 0 - 48 - 48 0 0 40 - 40 Typ - 24 + 5.0 0 0 0 -- -- -- -- -- -- -- -- -- -- -- -- Max - 21.6 + 5.5 + 10 + 7.0 + 10 47.5 -- 50 VDD 1.0 1.0 + 3.0 + 3.0 2.0 k 800 500 + 85 dBm A/A C mA Vdc mA Unit Vdc
External Transistor Beta Operating Ambient Temperature (See text for derating) All limits are not necessarily functional concurrently.
ELECTRICAL CHARACTERISTICS
(VEE = - 24 V, VDD = + 5.0 V, unless otherwise noted. VCC = VAG = VDG = 0 V, TA = 25C, see Figure 1.) Characteristic Symbol Min Typ Max Unit
POWER SUPPLIES
VEE Current On Hook (RL > 10 M, VEE = - 42 V) Off Hook (RL = 0 , VEE = - 42 V)* VDD Current On Hook (RL > 10 M, VDD = + 5.5 V) Off Hook (RL = 0 , VDD = + 5.5 V) VEE Ripple Rejection f = 1.0 kHz, @ VTX (4-wire) f = 1.0 kHz, @ Tip/Ring (2-wire) VDD Ripple Rejection f = 1.0 kHz, @ VTX (4-wire) f = 1.0 kHz, @ Tip/Ring (2-wire) * Includes loop current. mA IEEN IEEF IDDN IDDF PSRR 40 40 37 37 62 52 52 48 -- -- -- -- - 2.7 - 72 -- 4.0 - 1.0 - 55 1.4 7.0 -- - 41 2.7 14 dB
MC33121 2
MOTOROLA
ELECTRICAL CHARACTERISTICS
(VEE = - 24 V, VDD = + 5.0 V, unless otherwise noted. VCC = VAG = VDG = 0 V, TA = 25C, see Figure 1.) Characteristic Symbol Min Typ Max Unit
LOOP FUNCTIONS
Loop Current Maximum (RRF = 4.7 k, RL = 10 ) Nominal (RRF = 4.7 k, RL = 367 ) Minimum (RRF = 4.7 k, RL = 796 ) Battery Feed Resistance (RRF = 4.7 k, RL = 796 )* Hookswitch Threshold On-to-Off Hook Off-to-On Hook Fault Detection Threshold Ring-to-Ground (RL = 367 ) Tip-to-Battery (RL = 367 ) * Calculated from [(24/IL(min)) - 796] mA IL(max) IL IL(min) RBF RNF RFN RRG RTB 37 21 16 475 2.0 -- 600 600 41 27 17.5 575 4.1 7.7 1100 1100 51 34 -- 675 -- 10 -- -- k
GAIN LEVELS
Transmit Voltage Gain (CP, CN to TXO) Transmit Voltage Gain (VTX/VL) VL = 0 dBm, f = 1.0 kHz VL = 0 dBm, f = 3.4 kHz, with respect to GTX2 VL = + 3.0 dBm, f = 1.0 kHz, with respect to GTX2 VL = - 48 dBm, f = 1.0 kHz, with respect to GTX2 Transmit Distortion (at Pin 11) (f = 300 Hz to 4.0 kHz, - 40 dBm VT-R + 5.0 dBm) Receive Current Gain (IEP/IRXI) Receive Voltage Gain (VL/VRXI) (RL = 600 ) VRXI = 0 dBm, f = 1.0 kHz VRXI = 0 dBm, f = 3.4 kHz, with respect to GRX2 VRXI = + 3.0 dBm, f = 1.0 kHz, with respect to GRX2 VRXI = - 48 dBm, f = 1.0 kHz, with respect to GRX2 Receive Distortion (f = 300 Hz to 4.0 kHz, - 40 dBm VRXI + 5.0 dBm) Return Loss (Reference = 600 resistive, f = 1.0 kHz) Transhybrid Rejection (RL = 600 resistive, f = 1.0 kHz, Figure 4) GTX1 GTX2 -- - 0.3 - 0.1 - 0.15 -- -- GRX1 GRX2 94 - 0.3 - 0.1 - 0.15 -- -- 30 -- 0.328 0 0 0 0.1 0.05 102 0 0 0 0.1 0.05 > 40 44 -- 0.3 0.1 0.15 -- % -- 110 0.3 0.1 0.15 -- -- -- -- % dB dB mA/mA dB V/V dB
THDT
THDR RL THR
LONGITUDINAL SIGNALS (VCM = 1.0 Vrms, see Figures 1 and 2)
2-Wire Balance, f = 1.0 kHz, Zac = 600 (@ Tip/Ring) 4-Wire Balance, f = 1.0 kHz, Zac = 600 (@ VTX) 2-Wire Balance, f = 330 Hz, Zac = 600 (@ Tip/Ring) 4-Wire Balance, f = 330 Hz, Zac = 600 (@ VTX) 2-Wire Balance, f = 3.3 kHz, Zac = 600 (@ Tip/Ring) 4-Wire Balance, f = 3.3 kHz, Zac = 600 (@ VTX) 2-Wire Balance, f = 1.0 kHz, Zac = 900 (@ Tip/Ring) 4-Wire Balance, f = 1.0 kHz, Zac = 900 (@ VTX) Signal Balance, f = 1.0 kHz (Figure 3) Longitudinal Impedance, RS = 9100 Maximum Longitudinal Current, per side f = 1.0 kHz, ILoop = IL(min), CT = 0.1 F VEE = - 42, VCM = 5.12 Vrms ZLong ILong(max) 8.5 16 -- LB 58 58 58 58 53 53 -- -- 40 150 64 64 64 64 60 60 62 62 55 180 -- -- -- -- -- -- -- -- -- 210 mA dB
MOTOROLA
MC33121 3
ELECTRICAL CHARACTERISTICS
(VEE = - 24 V, VDD = + 5.0 V, unless otherwise noted. VCC = VAG = VDG = 0 V, TA = 25C, see Figure 1.) Characteristic Symbol Min Typ Max Unit
LOGIC INTERFACE
ST1 Output Voltage Low (IST1 = 1.0 mA, VDD = 5.5 V) High (IST1 = - 100 A, VDD = 4.5 V) ST2 Output Voltage Low (IST2 = 1.0 mA, VDD = 5.5 V) High (IST2 = - 100 A, VDD = 4.5 V) Time Delay Hookswitch Closure to ST1 Change Hookswitch Opening to ST1 Change Hookswitch Closure to 90% of Loop Current (CT = 0.1 F) PDI Taken High-to-Low to 10% of Loop Current PDI Taken Low-to-High to 90% of Loop Current PDI Input Current VPDI = 3.0 V, RL = 367 , VDD = 5.0 V VPDI = 0 V, RL = 367 , VDD = 5.5 V PDI Input Voltage Low High Vdc VOL VOH VOL VOH tST11 tST12 tHS tST21 tST22 IIH - 1250 -- VIL VIH VDG 2.0 - 800 - 800 -- -- - 300 -- Vdc 0.8 VDD VDG 2.4 VDG 2.4 -- -- -- -- -- 0.17 3.2 0.17 4.3 10 200 19 18 10 0.4 -- 0.4 -- s -- -- -- -- -- ms ms s A
MISCELLANEOUS
VQB Voltage (VQB - VEE) @ IL = 20 mA @ IL = 40 mA TXO Offset Voltage (VTXO - VAG) @ RL = 600 TXO Output Current RXI Offset Voltage (VRXI - VAG) @ RL = 600 VAG Input Current @ RL = 600 Idle Channel Noise (with C-message filter, RL = 600 ) @ TXO (Pin 11) @ Tip/Ring Thermal Resistance -- Junction to Ambient (Either package, in still air, soldered to a PC board) (@ TA = + 25C) (@ TA = + 85C) VQB -- -- VTXO ITXO VRXOS IVAG NIC4 NIC2 JA -- -- 62 36 -- -- - 400 275 -- -- -- -- 0.82 0.95 + 30 800 0.8 0.2 - 10 - 5.0 -- -- + 400 -- -- -- -- -- C/W mVdc A pk mVdc A dBrnc Vdc
MC33121 4
MOTOROLA
20
VCC EP
VDD 15 ST2/PDI 12
+ 5.0 V
IEP 0.01
19
PDI/ST2 CT 0.1 ST1
18 RP 100 IL TIP VL RL RING RP 0.01 100 RC 1.0 k RS 9.1 k RS 9.1 k RC 1.0 k 3 4 16 17
BP
ST1
13
CP
VDG VAG MC33121 RXI
14
TSI
9 IRXI 10 RRF 4.7 k RRO 20.3 k CRO 1.0 F 1.0 F +10.13 dB RRX 30.9 k
5
RSI
RECEIVE IN (VRXI)
CN
RFO
8
BN
TXO
11 2.0 k
TRANSMIT OUT (VTX)
2
EN
CF
7
1 - 24 V
VEE
VQB
6
301 CCF 1.0 F 20 CQB (10 F)
Components shown for a 600 system. Three grounds are connected directly together.
Figure 1. Test Circuit
VCM
368 0.01%
TIP MC33121 TEST CIRCUIT (FIGURE 1) VTX V4 4-Wire Balance = 20 (log V4/VCM) 2-Wire Balance = 20 (log V2/VCM) V2
2.0 F
368 0.01% 1.0 Vrms
RING
0 dB DIFF. AMPLIFIER
Figure 2. Longitudinal Balance Test (Per IEEE-455)
368 0.01%
TIP MC33121 TEST CIRCUIT (FIGURE 1) VRXI Vin 0 dBm 1.0 kHz
VB
368 0.01%
RING
Signal Balance = 20 (log VB/Vin)
Figure 3. Signal Balance Test
MOTOROLA
MC33121 5
MC33121 6
20 VCC EP 5.0 F MJD253 18 BP ST1 13 RC 17 CP 1.0 k, 2% RS 16 TSI MC33121 5 RSI RXI 10 RRF 4.7 k RFO 8 CRO 1.0 F TXO 11 30.6 k RRO RRX 20.3 k 15.8 k RTX1 10 k 2 EN CF 7 300 CCF (1.0 F) -24 V Component values shown for a 600 system. 0.1 1 VEE VQB 6 20 CQB (10 F) 1.0 F 600 0.005 600 9.1 k RING RS 9.1 k RC 4 CN 1.0 k, 2% MJD243 3 BN VEE CC 0.01 RP 100 VAG 9 VDG 14 CT ST1 ST2/PDI 12 VDD +5.0 V 15 19 CC 0.01 RP 100 ST2/PDI IL VEE TIP RECEIVE IN (VRXI ) RTX2 31.6 k - + TRANSMIT OUT (VTX )
Figure 4. Application Circuit
RL
MOTOROLA
PIN FUNCTION DESCRIPTION
Pin Symbol S bl VCC EP BP CP TSI VDD VDG ST1 ST2/PDI DIP 20 19 18 17 16 15 14 13 12 PLCC 28 27 26 24 23 22 20 18 17 Description D ii Connect to noise-free battery ground. Carries loop current and some bias currents. Connect to the emitter of the PNP pass transistor. Connect to the base of the PNP pass transistor. Connect to TIP through a current limiting protection resistor (RC). CP is the noninverting input to the internal transmit amplifier (Figure 28). Input impedance is 31 k. Sense input. Connect to TIP through a current limiting protection resistor (RS) which also sets the longitudinal impedance. Input impedance is to VCC.
[100
Connect to a + 5.0 V, 10% supply, referenced to digital ground. Powers logic section and provides some bias currents for the loop current drivers. Digital Ground. Reference for ST1, ST2 and VDD. Connect to system digital ground. Status Output (TTL/CMOS). Indicates hook switch status -- high when on-hook, low when off-hook, and pulse dialing information. Used with ST2 to indicate fault conditions. Status output and an input (TTL/CMOS). As an output, ST2 can indicate hook status -- Low when on-hook, high when off-hook. Used with ST1 to indicate fault conditions. As an input, it can be taken low (when off-hook) to deny subscriber loop current. Transmit voltage output. Amplitude is that across CP and CN. Nominally capable of 800 A output current. DC referenced to VAG. Receive current input. Current at this pin is multiplied by 102 at EP and EN to generate loop current. RXI is a virtual ground at VAG level. Current flow is out of this pin. Analog ground, reference for TXO and RXI. Connect to system analog ground. Current flow is into this pin. A resistor from this pin and RXI sets the maximum loop current and DC feed resistance. Minimum resistor value is 3.3 k (see Figures 5 to 7). A low leakage capacitor between this pin and VAG provides DC and AC signal separation. A series resistor is required for battery supply turn-on/off transient protection (Figure 4). Quiet Battery. A capacitor between VQB and VCC filters noise and ripple from VEE, providing a quiet battery source for the speech amplifiers. A series resistor is required for battery supply turn-on/off transient protection (Figure 4). Sense input. Connect to RING through a current limiting protection resistor which also sets the longitudinal impedance. Input impedance is to VQB.
TXO RXI VAG RFO CF VQB
11 10 9 8 7 6
16 14 13 12 10 8
[1/3
RSI CN BN EN VEE
5 4 3 2 1
7 6 4 3 2
[100
Connect to RING through a current limiting protection resistor. CN is the inverting input to the internal transmit amplifier (Figure 28). Input impedance is 31 k. Connect to the base of the NPN pass transistor. Connect to the emitter of the NPN pass transistor. Connect to battery voltage (- 21.6 V to - 42 V).
(Pins 1, 5, 9, 11, 15, 19, 21, and 25 are not internally connected on the PLCC package.)
MOTOROLA
MC33121 7
50 4700 IL, LOOP CURRENT (mA) 40 5100 6200 30 8200 20 10 k 10 0 400 800 1200 1600 2000 RL, LOOP RESISTANCE () 7500 RRF = 3900 RS = 9.1 k VEE = - 42 V TA = 25C
50 4700 IL, LOOP CURRENT (mA) 40 5100 6200 30 8200 20 10 k 7500 RRF = 3900 RS = 9.1 k VEE = - 28 V TA = 25C
10 0 200 400 600 800 1000 RL, LOOP RESISTANCE ()
Figure 5. Loop Current versus Loop Resistance and RRF
Figure 6. Loop Current versus Loop Resistance and RRF
50 4700 IL, LOOP CURRENT (mA) 40 5100 6200 30 7500 8200 20 10 k RRF = 3900 RS = 9.1 k VEE = - 24 V TA = 25C LOOP RESISTANCE THRESHOLD (k )
15 - 42 V VEE - 24 V 5.1 k RS 11 k 4.5 V VDD 5.5 V TA = 25C
13
11
9.0
7.0
10 0 200 400 600 800 1000 RL, LOOP RESISTANCE ()
5.0 3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
RRF (k)
Figure 7. Loop Current versus Loop Resistance and RRF
Figure 8. Off-Hook to On-Hook Threshold versus RRF
5.0 LOOP RESISTANCE THRESHOLD (k ) IDD, INTERNAL BIAS CURRENT (mA) 3.9 k RRF 10 k 4.5 V VDD 5.5 V TA = 25C
15
4.0
VEE = - 24 V
- 42 V VEE - 24 V TA = 25C VDD = + 5.0 V RRF = 4700
3.0 VEE = - 42 V 2.0
10
1.0 5.0
5.0 6.0 7.0 8.0 9.0 10 11 12 20 30 IL, LOOP CURRENT (mA) 40 45 RS, SENSE RESISTANCE (k)
Figure 9. On-Hook to Off-Hook Threshold versus RS
Figure 10. IDD versus Loop Current
MC33121 8
MOTOROLA
4.0 3.5 3.0 2.5 2.0 1.5 1.0 5.0 RING-TO-GROUND VEE = - 24 V TA = 25C RL = OPEN
3.0 VEE = - 42 V TA = 25C RING-TO-GROUND AND/OR TIP-TO-VEE 9.1 k 7.5 k
RLK , FAULT THRESHOLD (k)
RLK , FAULT THRESHOLD (k)
TIP-TO-VEE VEE = - 24 V TIP-TO-VEE VEE = - 42 V
2.4
1.8
1.2
RS = 11 k
5.1 k
0.6
RING-TO-GROUND VEE = - 42 V 7.0 9.0
0 11 0 500 1000 RL, LOOP RESISTANCE () 1500 2000
RS, SENSE RESISTANCE (k)
Figure 11. Fault Threshold (On-Hook) versus RS
Figure 12. Fault Threshold (Off-Hook) versus Loop Resistance
3.0 VEE = - 28 V TA = 25C RING-TO-GROUND AND/OR TIP-TO-VEE RS = 11 k 1.2 9.1 k
3.0 VEE = - 24 V TA = 25C RING-TO-GROUND AND/OR TIP-TO-VEE RS = 11 k 1.2 9.1 k 7.5 k 5.1 k
RLK , FAULT THRESHOLD (k)
RLK , FAULT THRESHOLD (k) 800
2.4
2.4
1.8
1.8
7.5 k 5.1 k
0.6 0 0 200 400 RL, LOOP RESISTANCE () 600
0.6 0 0 200 400 RL, LOOP RESISTANCE () 600
800
Figure 13. Fault Threshold (Off-Hook) versus Loop Resistance
Figure 14. Fault Threshold (Off-Hook) versus Loop Resistance
1.0 TA = 25C 200 < RL < 800 (SEE TEXT) RING-TO-VEE VEE = - 42 V RING-TO-VEE VEE = - 24 V TIP-TO-GROUND - 24 V VEE - 42 V
80 VEE = - 24 V TA = 25C 20 mA IL 40 mA
RLK , FAULT THRESHOLD (k)
RIPPLE REJECTION (dB)
0.8
4-WIRE 60 2-WIRE
0.6
0.4
40
0.2
0 5.0
7.0
9.0
11
20 0.02
0.1
1.0 f, FREQUENCY (kHz)
10
20
RS, SENSE RESISTANCE (k)
Figure 15. Fault Threshold (Off-Hook) versus RS
Figure 16. VDD Ripple Rejection versus Frequency
MOTOROLA
MC33121 9
80
80 VEE = - 24 V TA = 25C 20 mA ILOOP 40 mA 60
RIPPLE REJECTION (dB)
60
4-WIRE
2-WIRE 40 VEE = - 24 V TA = 25C 20 mA IL 40 mA CQB = 10 F 0.1 1.0 f, FREQUENCY (kHz) 10 20
RIPPLE REJECTION (dB)
1.0 kHz 300 Hz 4-WIRE 4.0 kfHz 1.0 kHz 300 Hz 2-WIRE 4.0 kHz
40
20 0.02
20 1.0
10
20
CQB, CAPACITOR (F)
Figure 17. VEE Ripple Rejection versus Frequency
Figure 18. VEE Ripple Rejection versus Frequency and CQB
0.6 0.5 VOL , OUTPUT VOLTAGE (V) 0.4 0.3 0.2 0.1 0 0 0.5 1.0 IOL, OUTPUT CURRENT (mA) 1.5 2.0 4.5 V VDD 5.5 V TA = 25C
6.0
VOH, OUTPUT VOLTAGE (V)
5.0 VDD = + 5.5 V 4.0 VDD = + 4.5 V 3.0 TA = 25C 2.0 0 -50 -100 -150 -200 IOH, OUTPUT CURRENT (A)
Figure 19. ST1, VOL versus IOL
Figure 20. ST1, VOH versus IOH
0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.25 0.50 0.75 1.0 IOL, OUTPUT CURRENT (mA) 4.5 V VDD 5.5 V TA = 25C
6.0
VOL , OUTPUT VOLTAGE (V)
VOH, OUTPUT VOLTAGE (V)
5.0
VDD = 5.5 V
4.0
VDD = 4.5 V
3.0 TA = 25C 2.0 0 -100 -200 -300 -400 -500 IOH, OUTPUT CURRENT (A)
Figure 21. ST2, VOL versus IOL
Figure 22. ST2, VOH versus IOH
MC33121 10
MOTOROLA
IC POWER DISSIPATION (W)
0.6
VEE = - 28 V TA = 25C VDD = + 5.0 V RRF = 3900 RRF = 6200
POWER DISSIPATION IN EACH TRANSISTOR (W)
0.7
0.4 VEE = - 28 V TA = 25C RP = 100 6.2 k 0.2 10 k 0.1 RRF = 3.9 k 0 0 200 400 RL, LOOP RESISTANCE () 600 800
0.3
0.5
0.4
0.3
RRF = 10 k
0.2 0 200 400 RL, LOOP RESISTANCE () 600 800
Figure 23. IC Power Dissipation versus Loop Resistance and RRF
Figure 24. Transistor Power Dissipation versus Loop Resistance and RRF
MAX. LONGITUDINAL CURRENT, PER LEG (mArms)
MAX. LONGITUDINAL CURRENT, PER LEG (mArms)
50
20 ST2 16 RT = 200 k f = 1.0 kHz 12 RT
40
VEE = - 28 V TA = 25C CT IL = 20 mA RS = 9.1 k
30 RS = 5.1 k 20 RS = 11 k 10 - 42 V VEE - 24 V f = 60 Hz AND 1.0 kHz CT > 0.1 F FOR 1.0 kHz CT > 1.0 F FOR 60 Hz 30 IL, LOOP CURRENT (mA) 40
RT = 200 k f = 60 Hz 8.0 RT = 20 k f = 1.0 kHz 4.0 RT = 20 k f = 60 Hz 0 0.1 1.0 CT (F) 10
0 20
Figure 25. Maximum Longitudinal Current versus Loop Current
Figure 26. Maximum Longitudinal Current versus CT, RT and Frequency
MOTOROLA
MC33121 11
FUNCTIONAL DESCRIPTION
Introduction The MC33121 is a solid state SLIC (Subscriber Line Interface Circuit) which provides the interface between the two wire telephone line and the four wire side of a Central Office or PBX. Most of the BORSCHT functions are provided, specifically: -- Battery feed of the loop current to the line, with programmable maximum current for short lines and battery feed resistance for long lines. -- Overvoltage protection through internal clamp diodes and external resistors and diodes. -- Supervision, in that hook status is indicated in the presence of 30 k leakage, and regardless of whether or not the circuit is powered down intentionally by the Central Office or PBX. Fault conditions are detected and indicated to the system. Dialing (pulse and DTMF) information is passed through the MC33121 to the 4-wire side. -- Hybrid function, in that the MC33121 is a 2-to-4-wire converter. Transmit, receive, return loss, and transhybrid gains are independently adjustable. Thy MC33121 does not provide ring insertion, ring trip, digital coding/decoding of the speech signals, nor test functions. These must be provided external to this device. The MC33121 controls two external transistors (one NPN and one PNP) through which the loop current flows. By appropriate circuit design, the power dissipation (which can
VCC MC33121 30 EP ILOOP 100 TIP RP BP - + 31 k 100 I A VDD 3060
exceed 3.0 W under certain worst case conditions) is approximately equally distributed among the two transistors and the IC, thereby lowering junction temperatures and increasing long term reliability. In most situations, heatsinks will not be required. The MC33121 incorporates critical sense resistors internally, which are trimmed for optimum performance. With this technique, the external resistors on the two wire side, which generally must be high wattage for transient protection reasons, can be non-precision. Longitudinal balance is tested to a minimum of 58 dB @ 1.0 kHz (refer to Electrical Characteristics and Figure 2) for both the two-wire and four-wire side, and typically measures in the mid-60s. The longitudinal current capability is tested to a minimum of 8.5 mArms per side (refer to Electrical Characteristics and Figure 2) at a loop current of 20 mA. Following is a description of the individual sections. Figure 4 is the reference schematic. DC Loop Current The DC loop current is determined by the battery voltage (VEE), the load resistance across Tip and Ring, and the resistor at RFO. Varying the 4 resistors RS and RC will influence the loop current a small amount (< 5%). The curves of Figures 5 to 7 indicate the loop current versus loop resistance, different values of RRF, and for various values of VEE. The graphs represent performance at TA = 25C and after the IC had reached a steady state temperature (> 5 minutes).
1.0 k 9.1 k 9.1 k 1.0 k
CP TSI RSI CN ICN ICP
CURRENT MIRROR IA
VDD + - VQB
VAG
ANALOG GROUND
RXI IRXI RRF
RL RING 100
RP ILOOP BN EN 30 3060 + -
12.4 k + - RFO
31 k
100
ICP
) ICN
3 VQB
5.0 IA = IRXI - 24 V VEE 0.8 V
10 F
Figure 27. DC Loop Current Path
MC33121 12
MOTOROLA
Figure 27 is representative of the DC loop current path (bold lines). On a long line (RL > 400 ), the loop current can be determined from the following equation:
I
+ RRFEE {(R ) 5) * 13} L )L
V
- 3.6 V * 13
(1)
protection needed, described in another section, with 1.0 k resistors being suitable for most applications. The resulting signal at TXO needs to be gained up to obtain 0 dB from Tip/ Ring to V TX (the 4-wire output). The common method involves an external op amp, as shown in Figure 28, with a gain of RTX2/RTX1. The gain from VL to VTX is: V TX V L * 0.328 + RTX2 ** 31 k ) 31 k) RTX1 (RC (3)
On short lines (RL < 400 ), the three diodes across the 12.4 k resistor clamp the voltage at RFO, thereby preventing the RXI current from increasing as the load resistance is decreased. The maximum loop current is: I L(max) V* + 1.85RRF 102 (T A
+ 25C) [400
(2)
If a codec/filter is used, many of which include an internal op amp, a separate op amp is not needed. CTX is primarily for DC blocking (of the TXO offset), and is usually large (1.0 F) so as to not affect the gain. Receive Path The receive path, shown in Figure 29, consists of the input at RXI, the transistor driver amplifiers, the external transistors, and the load at Tip/Ring. RXI is a virtual ground (DC level = VAG) and is a current input. Current flow is out of the pin. The RXI current is mirrored to the two transistor drivers which provide a gain of 102. the two external transistors are then two current sources, in series, operating at the same value. An additional internal circuit (not shown) balances the two current sources to maintain operation in their linear region. The load current (through RL) is slightly different from the transistor current due to the sense resistors RC and RS. The sense resistors add to the DC loop current, but subtract from the AC load current. In normal operation, the current at RXI is composed of a DC current (from RFO), an AC current (from VRX) which is the receive signal, and an AC current from TXO, which is the feedback signal to set the return loss (setting the return loss is discussed in the section on AC Terminating Impedance). The resulting AC signal at Tip is inverted from that at VRX, while the signal at Ring is in phase with VRX. The resistors RP are for transient protection, and their value (defined in another section) depends on the amount of protection required. A nominal value of 100 is suitable for most applications. The system receive gain, from VRX to Tip/Ring, is not described in this section since in normal applications, it involves the feedback which sets the AC terminating impedance. The Applications Section discusses these in detail.
Due to the temperature dependence of a diode's forward voltage, the maximum loop current will change with temperature by 0.3%/C. The battery feed resistance (VTIP/IL) is , but depends on the loop current, VEE, RRF, and is a valid parameter only on long lines where the current limit is not in effect. On short lines, the feed resistance is high since the loop current is clamped at a near constant level. The AC impedance (Return Loss) however, is not determined nor affected by the DC parameters. See the Applications Section for Return Loss information.
[-
Transmit Path The transmit path, shown in Figure 28, consists of an internal amplifier which has inputs at CP and CN, and its output at TXO. The gain is internally fixed at 0.328 V/V (- 9.7 dB). The output is in phase with the signal at CP (normally the same as TIP), and is out of phase with the signal at CN. The signal at TXO is also out of phase with that at VRX, the receive signal input, described in another section. The TXO output can swing Vp-p, with a nominal current capability of 800 A peak ( 275 A minimum). The load on TXO is the parallel combination of RTX1 and the RRO network (described later). TXO is nominally internally biased at the VAG DC level, but has an offset which varies with loop current. In normal applications, the signal at CP/CN is reduced slightly from that at Tip/Ring by the voltage divider composed of the external RC resistors, and the internal 31 k resistors. The value of the RC resistors depends on the transient
[3.0
TIP
1.0 k RC
CP 17
31 k AC VDD + - 31 k AC
9
VAG
VL 1.0 k RING RC CN 4
11 TXO RTX1 CTX
+ - RTX2 NOTE: Op amp may be part of a codec/filter.
VTX
AV = 0.328 VQB MC33121
Figure 28. Transmit Path
MOTOROLA
MC33121 13
Logic Interface (Hook status, pulse dialing, faults) The logic interface section provides hookswitch status, fault information, and pulse dialing information to the 4-wire side of the system at the ST1 and ST2 outputs. Figure 30 is a representative diagram. The logic outputs operate according to the truth table in Table 1: Table 1. Status Output Truth Table
Hook Status On-Hook Off-Hook On-Hook Off-Hook Fault Detection No Fault No Fault Fault Fault Outputs ST1 Hi Lo Lo Lo ST2 Lo Hi Lo Lo Circuit C di i Ci i Condition Internally powered down Powered up Internally powered down Internally powered down
current source pullup, and a 1.0 mA current source for a pulldown. Current limiting this output controls the discharge from the external capacitor when ST2 switches low. The condition where both ST1 and ST2 are high is not valid, but may occur momentarily during an off-hook to on- hook transition. The condition where both ST1 and ST2 are low may occur momentarily during an on-hook to off-hook transition -- this should not be interpreted as a fault condition. ST1 and ST2 are TTL/CMOS compatible and are powered by the + 5.0 V supply (VDD). Refer to the Applications Section for more details. Power Supplies, Grounds The MC33121 requires 2 power supplies: battery voltage between - 21.6 V and - 42 V (VEE), and an auxiliary voltage between + 4.5 V and + 5.5 V (VDD). VEE is nominally - 24 V, with a typical range of - 21.6 V to - 42 V, and must be referenced to VCC (battery ground). A 0.1 F bypass capacitor should be provided between VCC
Referring to Figure 30, ST1 is configured as an active NPN pulldown with a 15 k pullup resistor. ST2 has a 800 A
VCC 20 IT 30 EP 19 BP 18 TIP RP VL RL RING RP BN 3 EN 2 IT VQB 6 IA = IRXI 30 TO VEE + - + -
3060 IA MIRROR IA VDD + - 9 VAG 10 RXI VQB IRXI RRX
VRX
3060 MC33121
Figure 29. Receive Path
VDD 15 800 A TO LOOP CURRENT DRIVERS TIP RL RING RC RC RS RS CP CN TSI RSI FAULT DETECTION FAULT HOOK STATUS DETECTION 12 ST2/PDI BIAS CIRCUIT 50 k 1.0 mA CT OFF-HOOK ON-HOOK 50 k 5.0 F STATUS 2 EXTERNAL POWER DOWN CONTROL INPUT + 5.0 V
HOOK SWITCH
VDD 15 k 13 ST1 STATUS 1
14 VDG MC33121
Figure 30. Logic Interface
MC33121 14
MOTOROLA
and VEE. The VEE current (IEE) is nominally 1.0 mA when on-hook, 8.0 to 12 mA more than the loop current when off- hook, and mA when off-hook but powered down by using the PDI pin. Ripple and noise rejection from VEE is a minimum of 40 dB (with a 10 F capacitor at VQB), and is dependent on the size and quality of the V QB capacitor (CQB) since VQB is the actual internal supply voltage for the speech amplifiers. The absolute maximum for VEE is - 60 V, and should not be exceeded by the combination of the battery voltage, its tolerance, and its ripple. VDD is normally supplied from the line card's digital + 5.0 V supply, and is referenced to VDG (digital ground). A 0.1 F capacitor should be provided between VDD and VDG. The VDD current (IDD) is nominally 1.7 mA when on-hook and between 6.0 and 8.0 mA when off-hook (see Figure 10). When the MC33121 is intentionally powered down using the PDI pin, IDD changes by < 1.0 mA from the normal off-hook value.
[5.0
VAG is the analog ground for the MC33121, and is the reference for the speech signals (RXI and TXO). Current flow is into the pin, and is typically < 0.5 A. Normally, VCC, VDG and VAG are to be at the same DC level. However, if strong transients are expected at Tip and Ring, as in a Central Office application, or any application where the phone line is outdoors, VCC should not be connected directly to VDG and VAG in order to prevent possible damage to the + 5.0 V system. The MC33121 is designed to tolerate as much as 30 V between VCC and the other two grounds on a transient basis only. This feature permits VCC and the other grounds to be kept separate (on an AC basis) on the line card by transient suppressors, or to be connected together farther into the system (at the power supplies). See the Applications Section on ground arrangements and transient protection for further information on connecting the MC33121 to the system supplies.
APPLICATIONS INFORMATION
This section contains information on the following topics: Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Dissipation Calculations and Considerations . . . . . . . . . . . . . . . . . . . . . . . . . Selecting the Transistors . . . . . . . . . . . . . . . . . . . . . . Longitudinal Current Capability . . . . . . . . . . . . . . . . PC Board Layout Considerations . . . . . . . . . . . . . . . Alternate Circuit Configurations . . . . . . . . . . . . . . . . Design Procedure This section describes the step-by-step sequence for designing in the MC33121 SLIC into a typical line card application for either a PBX or Central Office. The sequence is important so that each new component value which is calculated does not affect components previously determined. Figure 4 (Typical Application Circuit) is the reference circuit for most of this discussion. The recommended sequence (detailed below), consists of establishing the DC aspects first, and then the AC aspects: 1) Determine the maximum loop current for the shortest line, select RRF. Power dissipation must be considered here. 2) Select the main protection resistors (RP), and diodes, based on the expected transient voltages. Transient protection configuration must also be considered here. 3) Select RC based on the expected transient voltages. 4) Select RS based on the desired longitudinal impedance at Tip and Ring. Transient voltages are also a factor here. 5) Calculate RRO based on the desired AC terminating impedance (return loss). 6) Calculate RRX based on the desired receive gain. 7) Calculate RTX2 and RTX1 based on the desired transmit gain. 8) Calculate the balance resistor (RB), or network, as appropriate for desired transhybrid rejection. 9) Logic Interface Preliminary There is a primary AC feedback loop which has its main sense points at CP and CN (see Figure 34). The loop extends from there to TXO, through RRO to RXI, through the internal amplifiers to the transistor drivers, through RP to Tip pg. 15 pg. 22 pg. 23 pg. 23 pg. 23 pg. 26 and Ring, and through the RCs to CP and CN. Components within this loop, such as RP, RC, the transistors, and the compensation capacitors need not be tightly matched to each other in order to maintain good longitudinal balance. The tolerance requirements on these components, and others, are described in subsequent sections. Any components, however, which are placed outside the loop for additional line card functions, such as test relay contacts, fuses, resistors in series with Tip and Ring, etc. will affect longitudinal balance, signal balance, and gains if their values and mismatch is not carefully considered. The MC33121 cannot compensate for mismatch among components outside the loop. The compensation capacitors (0.01 F) shown at the transistor collectors (Figure 4) compensate the transistor driver amplifiers, providing the required loop stability. The required tolerance on these capacitors can be determined from the following guidelines: * A 10% mismatch ( 5% tolerance) will degrade the longitudinal balance by dB on a 60 dB device, and by dB on a 70 dB device. * A 20% mismatch ( 10% tolerance) will degrade the longitudinal balance by dB on a 60 dB device, and by dB on a 70 dB device.
[3.0
[1.0
[6.0
[3.0
High quality ceramic capacitors are recommended since they serve the secondary function of providing a bleedoff path for RF signals picked up on the phone line. These capacitors should be connected to a good quality RF ground. The capacitors used at CQB and CF must be low leakage to obtain proper performance. Leakage at the CQB capacitor will affect the DC loop current characteristics, while leakage at the CF capacitor will affect the AC gain parameters, and possibly render the IC inoperative. 1) Maximum Loop Current and Battery Feed Resistance The maximum loop current (at RL = 0) is determined by the RRF resistor between RFO and RXI. The current limit is accomplished by three internal series diodes (see Figure 27) which clamp the voltage across RRF as the loop resistance decreases, thereby limiting the current at RXI. Since the loop current is 102 x IRXI, the loop current is therefore clamped. The graphs of Figures 5 to 7 indicate the maximum loop
MOTOROLA
MC33121 15
current at an ambient temperature of + 25C, and after the IC has reached thermal equilibrium (approx. 10 minutes). Although the maximum loop current is primarily a function of the RRF resistor, it is also affected by ambient temperature, and slightly by VEE. The ambient temperature effects are due to the temperature dependence of the diodes' forward voltage drop, causing the maximum loop current to change by 0.3%/C. Changing VEE affects the maximum current in that the power dissipation is changed, thereby changing the die temperature, which affects the diodes' voltage. The maximum loop current is affected slightly (< 5%) by the choice of the RS and RC resistors, since the sense currents through those resistors add to the current supplied by the transistors. The battery feed resistance is determined by RRF, and is not adjustable independently of the current limit. Defined as VTIP/IL, it is , and is a valid parameter only on long lines where the current limit is not in effect. On short lines, the feed resistance is high since the loop current is clamped at a near constant level. The AC impedance (Return Loss) however, is not determined nor affected by these DC parameters. Return loss is discussed in another section. If the application requires that the current limit value have a low temperature dependence, refer to the section following this design sequence which describes an alternate configuration.
[-
voltage across the transistors, which must be sufficient to handle the largest AC (transmit and receive) signals. If too large a value is selected for RP, the AC signals will be clipped. It is recommended that each transistor have no less than one volt (DC) across their collector to emitter. System AC specifications may require more than this. Since the RP resistors are within the loop, their tolerance can be 5% with no substantial degradation of longitudinal balance. A 10% tolerance (20% mismatch) will degrade balance by dB on a 65 dB device.
[4.0
Figure 31.
TIP 1.0 k RC CP VCC VEE 31 k AC VDD + - RING 1.0 k RC CN VCC VEE 31 k AC MC33121 VQB TXO AV = 0.328
[400
Figure 32. RC Protection Resistors 3) Selecting the RC Resistors The primary purpose of the RC resistors is to protect the CP and CN pins from transient voltages and destructive currents. Internally, these pins have clamp diodes to VCC and VEE rated for a maximum of 1.0 A under surge conditions only (Figure 32). The 1.0 k resistors shown in the figures, for example, will provide protection against surges up to 1.0 kV. Resistor manufacturers must be consulted for the proper type of resistor for this environment. The RC resistors are in series with internal 31 k resistors, and therefore form a voltage divider to the inputs of the transmit amplifier, as shown in Figure 32. This will affect the transmit gain, receive gain, return loss, and transhybrid rejection (described in subsequent sections). The tolerance of the RC resistors depends on the value selected for them, since any mismatch between them will create a differential voltage at CP and CN when longitudinal voltages are present on Tip and Ring. To ensure a minimum of 58 dB of longitudinal balance, the resistors' absolute value must not differ by more than 39 . With a nominal value of 1.0 k, their tolerance must be 2%, or less. If their nominal value is 390 or less, their tolerance can be 5%. 4) Longitudinal Impedance (ZLong) -- Selecting the RS Resistors The longitudinal impedance is determined by the RS resistors at the TSI and RSI pins according to the following equation: R 100 S (4) Z Long 51 ZLong is defined as VLong/ILong as shown in Figure 33; for R S = 9.1 k , Z Long = 180 . The calculated value of ZLong includes the fact that the RS resistors are in parallel with the synthesized impedance. The tolerance of the RS resistors therefore depends on how much mismatch can be tolerated between the longitudinal impedances at Tip and at Ring. Calculations indicate the two RS resistors can have a 5% tolerance, and still comfortably provide a minimum of 58 dB longitudinal balance.
2) Main Protection Resistors (RP) and Transient Currents The purpose of the protection resistors (RP), along with the 4 clamp diodes shown in Figure 4, is to absorb the bulk of the transient energy when transient voltages come in from the phone line. The resistor value must be selected to limit the transient current to a value which can be tolerated by the diodes, while dissipating the energy. The recommended value shown (100 ) will limit the current from a 1500 V transient to 15 A, which can be carried by 1N4002 diodes under surge conditions. The resistors must be of a type which can tolerate the high instantaneous energy associated with transients. Resistor manufacturers should be consulted for this information. Referring to Figure 4, a positive transient on either Tip or Ring, or both, will cause the transient current to be delivered to Ground. A negative transient will cause the transient current to come from the VEE supply line. Therefore, the PC board track supplying VCC and VEE to the MC33121 must be designed to carry the transient currents as well as the normal operating currents. Additionally, since a negative transient will cause a current flow out of the power supply's negative output, which is opposite to the normal flow of current, provisions must be made for this reverse current flow. One suggested method is to place a zener transient suppressor (1N6287 for - 42 V, 1N6282 for - 28 V and - 24 V) across the battery supply pins (VCC to VEE) physically adjacent to the MC33121. The inductance associated with PC board tracks and wiring will result in insufficient protection for the MC33121 if the suppressor is located at the opposite end of the line card, or at the power supplies. Transient currents can be reduced by increasing the value of RP, with an upper limit determined by the DC conditions on the longest line (highest loop resistance) and minimum VEE supply voltage. These conditions determine the minimum DC
+)
MC33121 16
MOTOROLA
The resistors must be able to withstand transient voltages expected at Tip and Ring. The TSI and RSI pins have internal clamp diodes rated for a maximum of 1.0 A under surge conditions only (Figure 33). Resistor manufacturers must be consulted for the proper type of resistor for this environment. 5) AC Terminating Impedance and Source Impedance (Zac) -- Return Loss The return loss measurement is a measure of how closely the AC impedance of the SLIC circuit matches the characteristic impedance of the phone line, or a reference imped-
ance. The reference impedance can be, in some cases, a pure resistance (commonly 600 or 900 ), a series resistor and capacitor (900 + 2.16 F), or a more complex network. To achieve proper return loss with the MC33121, the RRO impedance shown in Figure 34 is to have the same configuration as the reference impedance, but with values scaled according to the equations mentioned below. CRO, used primarily for DC blocking, is generally a large value (1.0 F) so as to not affect the impedance of RRO. However, it can be included in the RRO network if a complex network is required.
VCC EP ZLONG TIP ILONG BP VCC 7.0 V 100 COMMON MODE DETECTOR & AMPLIFIER VQB BUFFER
RS
TSI
RING VLONG AC
ILONG ZLONG
RS
RSI VEE 14 V
100
BN EN VEE
BUFFER MC33121
- 24 V
Figure 33. Longitudinal Impedance
VCC 30 IT ZT 2 TIP IL VL ZAC RS 9.1 k RC 1.0 k RING ZT 2 IT VQB 30 TO VEE 3060 RP 100 RP 100 RS 9.1 k RC 1.0 k EP BP - + 31 k IA AC AC 31 k + - + - AV = 0.328 AC TXO CRO + - IA MIRROR VAG IRXI RXI RRO 3060
CP TSI RSI CN BN EN
MC33121
IA = IRXI
Figure 34. AC Terminating Impedance
MOTOROLA
MC33121 17
Zac is the impedance looking into the circuit from Tip and Ring (set by RRO), and is defined as VL/IL. Half of Zac is from Tip to VCC, and the other half is from Ring to VQB (an AC ground). Each half is made up of a synthesized impedance (ZT/2) in parallel with RS and (RC + 31 k). Therefore, Zac is equal to: Zac = [ZT/2//RS//(RC + 31 k)] * 2 (5) and Z T 2 {R + {R S S
SF
[(RC k) RS] 1.037 + (RC ) 31 ) 31[(RC ) 31*k) R *-106ac 2)] k) * (Z S
(9)
Zac is computed at a nominal frequency of interest. A first order approximation of Equation 9 is: SF = 1.037 * 106/(RC + 31 k) For example: (9a)
) 31 k)} * (Zac 2) (RC ) 31 k)} - (Z ac 2)
(RC
(6)
IF THE AC LOAD IS: THEN RRO SHOULD BE: TO RXI 2.16 F 900 TO TIP AND RING FROM TXO 31.15 k (RRO) 62 nF (CRO)
The synthesized impedance ZT is created as follows: An incoming signal VL produces a differential voltage at CP and CN, and therefore at TXO equal to: V * 31 * + VL (RC )k31 0.328 TXO k) (7)
The signal at TXO creates an AC current IRXI through RRO. RXI is a virtual ground, and CRO is insignificant for first order calculations. IRXI is gained up by a factor of 102 to produce the current IT through the transistors. ZT is therefore VL/IT. The relationship between ZT and RRO is: RRO
IF THE AC LOAD IS: 820 220
THEN RRO SHOULD BE: TO RXI
0.115 F
TO TIP AND RING FROM TXO
3.3 nF
28.4 k 7.61 k
CRO
+ ZT(31 k ) RC)
* 1.037 * 10 6
(8)
While equation 8 gives the exact value for RRO, a first order approximation is Zac * 33.5. a) Resistive Loads (with RC = 1.0 k, RS = 9.1 k): For a 600 resistive system, ZT calculates to 626 , and RRO calculates to 20.3 k . For a 900 resistive system, ZT calculates to 961 , and RRO calculates to 31.14 k . b) Complex Loads For complex (nonresistive) loads, the MC33121 must be made to look like a termination impedance equal to that complex load. This is accomplished by configuring RRO the same as the complex load, but with all impedance values increased according to the scaling factor of Equation 9.
CRO must remain in series with the network to provide DC blocking. If the load network does not include a series capacitor (as in the second example above), CRO should be large (1.0 F) so its impedance does not affect the RRO network. The above procedure will yield a return loss measurement which is constant with respect to frequency. The RRO resistor, or network, must have a tolerance equal to or better than the required system tolerance for return loss and receive gain. 6) Receive Gain (GRX) The receive gain involves the same circuit as Figure 34, but with the addition of the RRX resistor (or network) which sets the receive gain. See Figure 35.
EP BP RP 100 IL VL RAC RS 9.1 k RING RP 100 RC 1.0 k RSI RRO CN BN EN TXO CRO ITXO VAG
TIP
RC 1.0 k RS 9.1 k
CP TSI MC33121 RXI IRXI RRX VRX IR
Figure 35. Receive Gain
MC33121 18
MOTOROLA
The receive gain (GRX), defined as the voltage gain from VRX to VL, is calculated as follows: RXI is a virtual ground, and Rac is the AC impedance of the load (phone line). The AC current generated in the transistors is 102 * IRXI, which is equal to 102 * (IR - ITXO). IR = VRX/RRX, and I TXO V 0.328 L + VTXO + RRO* *31 k * ) RC) (31 k RRO (10)
The preceding procedure will yield a receive gain which is constant with respect to frequency. The RRX resistor, or network, must have a tolerance equal to or better than the required system tolerance for receive gain. 7) Transmit Gain (GTX) Setting the transmit gain involves selecting RTX1 and RTX2 in Figure 28. The voltage gain from VL to VTX is calculated from the following: G * 0.328 + VVTX + RTX2 ** 31 k ) 31 k) TX RTX1 (RC L (15)
Using equations 5 and 8, involving Zac, RS and RC, and the above equations yields: V V L
RX
+ GRX + 102 * (Rac RRX
(R + 102 * G ac Z ac) RX
Z ac)
(11)
Therefore, RRX
(12)
Equation 12 applies only for the case where Rac and Zac have the same configuration. If they also have the same magnitude, then set RRX = 51 * Rac to set a receive gain of 0 dB. The AC source impedance of the above circuit to Tip and Ring is Zac. For the case where Rac Zac, use the following equation: V V L
RX
+
RRX * 1 Z L
102
(13)
)
S
1.037 * 10 6 (31 k)RC) * RRO (RC
where Z
L
+
R ac 2
R
) 31 k)
*2
(14)
a) Resistive Loads For a 600 resistive system, set RRX = 30.6 k , and for a 900 resistive system, set RRX = 45.9 k . b) Complex Loads For complex (nonresistive) loads, the RRX resistor needs to be replaced with a network having the same configuration as the complex load, but with all impedance values scaled up by a factor of 51 (for 0 dB gain). If a gain other than 0 dB is desired, the scaling factor is determined from Equation 12. This method applies only if the RRO network has been made complex comparable to the load according to the procedure in the previous section (Equations 5 - 9a), such that Rac = Zac. Using a scaling factor of 51, and the previous examples, yields:
IF THE AC LOAD IS: 2.16 F 900 TO RXI THEN RRX SHOULD BE: VRX 45.9 k 42 nF
For 0 dB gain, set RTX2 = 3.15 x RTX1 (for RC = 1.0 k). The actual values of RTX2 and RTX1 are not critical -- only their ratio so as to provide the proper gain at the op amp. Once the ratio is established, the two resistors can be selected from a set of standard resistor values. The minimum value for RTX1 is limited by the drive capability of TXO, which is a nominal 800 A peak ( 275 A minimum). As a general rule, RTX1 should be between 5.0 k and 20 k . The load on TXO is the parallel combination of RTX1 and RRO. CTX is for DC blocking, and is typically a large value (1.0 F) so as to not be a significant impedance. In general, it should not be used for low frequency rolloff as that will affect the transhybrid rejection (discussed in the next section). Low frequency rolloff should be done after the op amp. High frequency roll-off can be set by placing a capacitor across RTX2. For complex loads (at Tip and Ring), if RRO and RRX have been made complex comparable to the load as described in the previous sections, neither RTX1 nor RTX2 needs to be complex since both the transmit and receive signals which appear at TXO will be flat with respect to frequency. RTX1 and RTX2 must have a tolerance equal to or better than the required system tolerance for the transmit gain. 8) Balance Network (RB) -- Transhybrid Rejection When a receive signal is applied to VRX to produce a signal at Tip and Ring, the two-to-four wire arrangement of a hybrid (the MC33121) results in a reflected signal at TXO. Transhybrid rejection involves canceling that reflected signal before it appears at VTX. The method used is to insert the RB resistor (or network) as shown in Figure 36. The current IB, supplied from VRX, cancels the current ITX1 supplied from TXO (Node A is a virtual ground). Good transhybrid cancellation requires that the currents be equal in magnitude and 180 out of phase at Node A. Using the equations for transmit and receive gains, the current ITX1 is equal to: I *V * 31 ac * + RRX 33.5ac )RX ]* *ZRTX1Z*L (RC )k31 k) TX1 * [Z Z L (16)
TO TIP AND RING
IF THE AC LOAD IS: 820 220 0.115 F TO TIP TO AND RING RXI
THEN RRX SHOULD BE: 2.25 nF VRX
a) For the case where RRO and RRX are comparable in configuration to Z: Since IB = VRX/RB, then RB can be determined from: RB (RC 31 + RRX * *RTX1 * Z ] *)31 k k) 33.5 [Z ac L (17)
11.2 k 41.8 k
MOTOROLA
MC33121 19
TIP RXI -102 IRX VL ZL Zac + - RING MC33121 VL x 0.328 TXO RTX1 ITX1 A RRX IB RB RTX2 - + IRX VRX
VTX
Figure 36. Balance Resistor
Equation 17 provides a value for an RB resistor which will provide the correct magnitude for IB. The correct phase relationship is provided by the fact that the signal at TXO is out of phase with that at VRX. The phase relationship will be 180 only if RRO and RRX are of a configuration identical to that of the load. This applies regardless of whether the load, ZL, (and RRO and RRX) are purely resistive or of a complex nature. Equation 17 reduces to a non-complex resistance if RRX, Zac, and ZL are all comparably complex. For the case where Zac = ZL, RRX = 51 * Zac, and RC = 1.0 k, Equation 17 reduces to: RB = 3.15 * RTX1 (18)
explanation, the current source and Zac of Figure 36 are replaced with the Thevenin voltage source and series Zac. Since ZL and Zac are not matched, there will be a phase shift from VRX to the signal across Tip and Ring. This phase shift is also present at TXO. The same phase shift is generated at node B in the RB network by making RB1 equal to Zac, and ZL equal to the load. RB2 is then calculated from: RRX * RTX1 * (RC 31 k) (19) RB2 33.5 * Z ac * 31 k
+
)
b) For the case where Zac and ZL do not have the same frequency characteristics: For the case where, for reasons of cost and/or simplicity, the load (RL) is considered resistive (whereas in reality it is not a pure resistance) and therefore resistors, rather than networks, were selected for RRO and RRX, using a simple resistor for RB may not provide sufficient transhybrid rejection due to a phase angle difference between VRX and TXO. The terminating impedance may therefore not necessarily be matched exactly to the line impedance, but the resulting circuit still provides sufficiently correct performance for receive gain, transmit gain, and return loss. The rejection can be improved in this case by replacing RB with the configuration shown in Figure 37. Even on a very short phone line there is a reactive component to the load due to the two compensation capacitors (CC, Figure 4) at the transistor collectors. The two capacitors can be considered in series with each other, and across the load as shown in Figure 37. To simplify the
For example, for a system where the load is considered a 600 resistor (RRO = 20.3 k , RRX = 30.6 k , RTX1 = 10 k , and RC = 1.0 k), RB1 would be a 600 resistor, ZL (in the RB network) would be a 600 resistor in parallel with a 0.005 F capacitor, and RB2 calculates to 15.715 k . The RB resistor, or network, must have a tolerance equal to or better than the required system tolerance for transhybrid rejection. 9) Logic Interface The logic circuit (output ST1, and the I/O labeled ST2/PDI) is depicted in Figure 30, and functions according to the Status Output Truth Table (Table 1). a) Output Characteristics ST1 is a traditional NPN pull-down with a 15 k pull-up resistor. Figures 19 and 20 indicate its output characteristics. ST2 is configured with the following items: a) a 1.0 mA current source for a pull-down which is active only when ST2 is internally set low; b) an 800 A current source pull-up which is active only when ST2 is internally set high; c) a positive
TIP Zac VL Rac ZL RING MC33121 0.005 F
RXI RRX VS + - TXO RTX1 ITX1 RB1 B IB RB2 ZL
VRX
RB
RTX2 - +
A
VTX
Figure 37. Balance Network
MC33121 20
MOTOROLA
feedback aspect within this output circuit which provides considerable hysteresis for stability reasons. Its output characteristics are shown in Figures 21 and 22. Due to this configuration, any external pull-up resistance which is applied to this pin must be greater than 15 k , or the output may not reliably switch from high to low. Any external pull- down resistance does not affect this output's ability to switch from low-to-high, but does affect the maximum longitudinal currents which can be accepted by the circuit (see the section on Longitudinal Current Capability). The capacitor (CT) is required to provide a time delay, for stability reasons, during transitions between off-hook and on-hook. This capacitor additionally affects maximum longitudinal currents, as well as stability during pulse dialing (explained below). b) Hook Status The MC33121 uses the sense currents at CP and CN to activate the hook status circuit. The sensing is configured such that the circuit monitors the impedance across Tip/Ring, which results in the hookswitch thresholds are minimally affected by the battery voltage. The off-hook to on-hook threshold is affected by the choice of RRF according to the graph of Figure 8, but is not affected by the value of RS. The on-hook to off-hook threshold is affected by the value of RS according to the graph of Figure 9, but is not affected by RRF. Varying the RC resistors does not affect the thresholds significantly. When the telephone is on-hook (ST1 = High, ST2 = Low), the MC33121 is internally powered down, the external transistors are shut off, and power consumption is at a minimum. Upon closure of the phone's hookswitch, ST1 will switch low within 10 s. ST2 will then change state slowly due to the external capacitor (CT = 5.0 F). There is a ms delay for ST2 to reach the threshold necessary to activate the internal bias circuit, which in turn activates the external drive transistors to supply loop current. This delay is necessary to prevent instabilities during the transition to off-hook. Upon opening the telephone's hookswitch, ST1 will switch high within s. ST2 then requires ms to reach the threshold to switch off the internal bias circuit, which in turn shuts down the external drive transistors.
c) Pulse Dialing During pulse dialing, ST1 will change state concurrent with the hookswitch. ST2 is kept from switching during pulse dialing by the external capacitor (CT), which keeps the MC33121 in a powered up condition and stable. If the CT capacitor is too small, the voltage at ST2 could drop to the PDI threshold (see section e below) during each pulse. This could cause the MC33121 to create additional noise on the line as it would cycle between a power-up and power-down condition with each dialing pulse. d) Fault Detection Faults are defined as excessive leakage from Tip to VEE and/or ground, and from Ring to VEE and/or ground. A single fault is any one of the above conditions, while a double fault is defined as excessive leakage from Tip to VEE and from Ring to VCC, as depicted in Figure 38. Refer to Figures 11 - 15 for the resistance, RLK, which will cause the MC33121 to switch to a power-down condition. If the leakage resistance is less than that indicated in the graphs, the MC33121 will power-down itself and the two external transistors, thereby protecting them from overheating. Both status outputs (ST1 and ST2) will be at a logic low, indicating a fault condition. A fault condition is detected by monitoring an imbalance in the magnitudes of the currents at TSI and RSI, and/or a polarity reversal at Tip and Ring. The MC33121 will detect the following conditions: 1) When on-hook (see Figure 11): a) < 2.6 k between Ring and VCC (depending on RS and VEE), with no hysteresis at this threshold, or b) < 3.7 k between Tip and VEE (depending on RS and VEE), with no hysteresis at this threshold, or c) Both a and b simultaneously. Leakage from Tip to VCC and/or Ring to VEE are not detected as faults while the MC33121 is on-hook. 2) When off-hook (367 between Tip and Ring): a) < 400 between Tip and VCC (RS = 6.2 k), or b) < 1800 between Tip and VEE, or c) < 400 between Ring and VEE (RS = 6.2 k), or d) < 1800 between Ring and VCC, or e) Both b and d simultaneously
[8.0 [60
[200
ON-HOOK VCC MC33121 RLK TIP AND/OR =0 ST2 RLK VEE VEE RING
OFF-HOOK VCC MC33121 RLK TIP AND/OR ST1 ST1 RL RLK VEE VEE RING
OFF-HOOK VCC MC33121 RLK TIP ST1 OR =0 ST2 RL RLK VEE VEE RING =0 ST2
Figure 38. Fault Detection
MOTOROLA
MC33121 21
A simultaneous occurrence of conditions a) and c) is not detected as a fault. See Figures 12 to 15 for the threshold variation with RL and VEE. Resetting of the fault detection circuit requires that the leakage resistance be increased to a value between 10 k and 20 k , depending on VEE, RL, and RS. Both ST1 and ST2 should be monitored for hookswitch status to preclude not detecting a fault condition. Figure 15 indicates the variation in fault thresholds for Tip- to-VCC and Ring-to-Battery faults, and is valid only for loop resistances of 200 to 800 . On loops larger than 800 , the MC33121 does not reliably indicate the fault condition at ST1 and ST2, but may indicate on-hook status instead. This does not apply to Tip-to-Battery and Ring-to-VCC faults which are correctly detected for lines beyond 800 . e) PDI Input The ST2 output can also be used as an input (PDI Input) to power down the circuit, denying loop current to the subscriber (by shutting off the external pass transistors), regardless of the hookswitch position. Powering down is accomplished by pulling PDI to a logic low with an open collector output, or an NPN transistor as shown in Figure 30. The switching threshold is V. The current out of PDI, when pulled low, is A. Releasing PDI allows the MC33121 to resume normal operation. If the external telephone is off-hook while the MC33121 is powered down, sense currents at CP and TSI will result in some loop current flowing through the loop and back into CN and RSI. This current is generally on the order of 1.0 to 3.0 mA, determined primarily by the RS resistors, loop resistance, and VEE. ST1 will continue to indicate the telephone's actual hook status while PDI is held low. The on-to-off hook threshold is the same as that during normal operation, but the off-to-on hook threshold is > 250 k . When powered down with the PDI pin, the receive gain (VRXI to Tip/Ring) is muted by > 90 dB, and the transmit gain (Tip/Ring to TXO) is muted by > 30 dB.
Based on the results of almost ten years of + 125C operating life testing, Table 2 has been derived indicating the relationship between junction temperature and time to 0.1% wire bond failure. Table 2. Statistical Lifetime
Junction Temperature (C) 80 90 100 110 120 130 140 Time (Hours) 1,032,200 419,300 178,700 79,600 37,000 17,800 8,900 Time (Years) 117.8 47.9 20.4 9.4 4.2 2.0 1.0
Motorola MECL Device Data, DL122
[800
[1.5
The "Time" in Table 2 refers to the time the device is operating at that junction temperature. Since the MC33121 is at a low power condition (nominally 40 mW) when on-hook, the duty cycle must be considered. For example, if a statistical duty cycle of 20% off-hook time is used, operation at 130C junction temperature (when off-hook) would result in a statistical lifetime of years.
[10
b) Power and Junction Temperature Calculation The power within the IC is calculated by subtracting the power dissipated in the two-wire side (the transistors and the load) from the power delivered to the IC by the power supplies. Refer to Figure 4 and 27. PD = |VDD * IDD| + |VEE * IEE| - (IL * |VEP - VEN|) (20)
The terms VEP and VEN are the DC voltages, with respect to ground, at the EP and EN pins. These voltages can be measured, or can be approximated by: VEN VEP [- (30 * IL) [|VEE| + 2.1 V + (IL * 35 )
Power Dissipation, Calculation and Considerations a) Reliability The maximum power dissipated by the MC33121 must be considered, and managed, so as to not exceed the junction temperature listed in the Maximum Ratings Table. Exceeding this temperature on a recurring basis will reduce long term reliability, and possibly degrade performance. The junction temperature also affects the statistical lifetime of the device, due to long term thermal effects within the package. Today's plastic integrated circuit packages are as reliable as ceramic packages under most environmental conditions. However, when the ultimate in system reliability is required, thermal managements must be considered as a prime system design goal. Modern plastic package assembly technology utilizes gold wire bonded to aluminum bonding pads throughout the electronics industry. When exposed to high temperatures for protracted periods of time an intermetallic compound can form in the bond area resulting in high impedance contacts and degradation of device performance. Since the formation of intermetallic compounds is directly related to device junction temperature, it is incumbent on the designer to determine that the device junction temperature is consistent with system reliability goals.
Refer to Figure 23. The junction temperature is then calculated from: TJ = TA + (PD * JA) (21) where TA is the ambient air temperature at the IC package, and JA is the junction-to-ambient thermal resistance shown in Figure 39. The highest junction temperature will occur at maximum VEE and VDD, maximum loop current, and maximum ambient temperature. If the above calculations indicate the junction temperature will exceed the maximum specified, then it is necessary to reduce the maximum loop current, ambient temperature, and/or VEE supply voltage. Air flow should not be restricted near the IC by tall components or other objects since even a small amount of air flow can substantially reduce junction temperature. For example, typically an air flow of 300 LFPM (3.5 mph) can reduce the effective JA by 14 to 20% from that which occurs in still air. Additionally, providing as much copper area as possible at the IC pins will assist in drawing away heat from within the IC package. For additional information on this subject, refer to the "Thermal Considerations" section of Motorola MECL System Design Handbook, and the "System Design Considerations" section of Motorola MECL Device Data.
MC33121 22
MOTOROLA
70 MC33121 STILL AIR, SOLDERED TO A G-10 PC BOARD
measure the conditions on the transistors during the worse case fault(s). Table 3. Transistor Power During a Fault
VEE RL 150 150 600 600 PPNP 0.835 0.257 0.601 0.109 PNPN 0.615 0.176 0.185 0.057
60 JA, C/W
50
- 42 - 24 - 42 - 24
40
30 25 35 45 55 TA, C 65 75 85
Figure 39. Thermal Resistance (Junction-to-Ambient) Selecting the Transistors The specifications for the two loop current pass transistors involve their current gain, voltage rating, and power dissipation capabilities at the highest ambient temperatures. Power dissipation during both normal operation and faults must be considered when determining worst case situations. Generally, more power is dissipated during a fault condition than during normal operation. The transistors' minimum beta is recommended to be 40 at the loop currents involved in the application. A lower beta could degrade gain and balance performance. Maximum beta should be less than 500 to prevent possible oscillations. Darlington type transistors should not be used. The voltage rating should be consistent with the maximum VEE, expected transients, and the protection scheme used. Referring to Figure 27, during normal operation the loop current and the voltage across the transistors are both at a maximum when the load impedance (RL) is at a minimum. The loop current is determined by RRF and the graphs of Figures 5 - 7. The voltage across each transistor is determined from the following: V - 2.1 - [(65 2RP R ) * I ] EE L L (22) T 2 The power in each transistor is then (VT * IL). The voltage across the two transistors will always be nearly equal during normal operation, resulting in equal power dissipation. The graph of Figure 24 indicates the power dissipated in each transistor where RP = 100 . During a fault condition, depicted in Figure 38, if the leakage resistance from Tip to VEE or from Ring to VCC is less than that shown in Figures 12 - 14 (when off-hook), the MC33121 will power down the transistors to protect them from overheating. Should the leakage resistance be slightly higher than that shown in the graphs, however, and the fault detection has not been activated, the power in one transistor (in a single fault, both transistors in a double fault) will be higher than normal. The power will depend on VEE, RL, RP and the leakage resistance. Table 3 is a guide of the power in the transistor dissipating the higher power level. The power (in watts) in the two right columns indicates the power dissipated by that transistor if it is carrying the maximum fault current. The system designer should attempt to predict possible fault conditions for the system, and then V
For most applications involving a maximum loop current of 30 - 40 mA, and a maximum TA of + 85C, and where faults may occur, the MJD243 and MJD253 DPAK transistors are recommended. When mounted as described in their data sheet, they will handle both the normal loop current as well as most fault conditions. If faults are not expected to occur in a particular application, then smaller package transistors, such as MPS6717 and MPS6729, may be used. Each application must be evaluated individually when selecting the transistors. Other possible transistors which can be considered:
PNP MJD253-1 MJE253 MJD32 MJD42 MJD350 TIP30A,B,C NPN MJD243-1 MJE243 MJD31 MJD41 MJD340 TIP29A,B,C
Longitudinal Current Capability The maximum longitudinal current which can be handled without distortion is a function of loop current, battery feed resistance, the longitudinal impedance, and the components on ST2. Since the pass transistors cannot pass current in the reverse direction, the DC loop current provides one upper boundary for the peak longitudinal current plus peak speech signal current. The battery feed resistance determines, in effect, the DC voltage across the transistors, which is a measure of the headroom available for the circuit to handle the peak longitudinal voltage plus peak speech signal voltage. The longitudinal impedance, determined by the RS resistors (equation 4), determines the longitudinal current for a given longitudinal voltage. While analysis of the above items may yield one value of maximum longitudinal current, a different limit (which may be higher or lower) is imposed by the capacitor CT, and any pulldown resistance RT, on Pin 12 (ST2). This is due to the fact that the sense currents at TSI and RSI will be alternately mismatched as Tip and Ring move up and down together in the presence of longitudinal signals. When the longitudinals are strong, the internal fault detect circuit is activated with each 1/2 cycle, which attempts to switch ST2 low (see the section on Fault Detection). The speed at which ST2 can switch low is a function of both the external capacitor, CT and any pulldown resistance, RT. The graphs of Figures 25 and 26 indicate the maximum longitudinal current which can be handled (in Tip and in Ring) without distortion or causing ST2 to switch low. PC Board Layout Considerations PC board considerations include thermal, RFI/EMI, transient conditions, interconnection of the four wire side to the
+
)
)
MOTOROLA
MC33121 23
codec/filter, and others. Wirewrapped boards should be avoided -- breadboarding should be done on a (at least) reasonably neat PC board. a) Thermal Power dissipated by the MC33121 and the two transistors must be removed to prevent excessively high junction temperatures. The equations for calculating junction temperatures are mentioned elsewhere in this data sheet. Heat is removed by both air flow and copper foil on the PC board. Since even a small amount of air flow substantially reduces junction temperatures compared to still air, tall components or other objects should not be placed such that they block air flow across the heat generating devices. Increasing, wherever possible, the area of the copper foil at the IC pins will provide additional heat removal capability. A ground plane can generally help here, while at the same time helping to reduces RFI problems. b) RFI/EMI While the MC33121 is intended for use at audio frequencies, the internal amplifiers have bandwidths in excess of 1.0 MHz, and can therefore respond to externally induced RFI and EMI. Interference signals can come in on the phone line, or be radiated on to the PC board from nearby radio stations or from high frequency circuitry (digital & microprocessor circuitry) in the vicinity of the line card. Usually RFI entering from the phone line at Tip and Ring can be removed by the compensation capacitors (CC) provided they are connected to a good quality RF ground (generally the same ground which connects to V CC on the MC33121). The ground track should be as wide and as direct as possible to minimize lead inductance. Generally better results can be obtained if an RF bleedoff to earth (or chassis)
VCC EP BP
ground can be provided where the twisted pair phone line comes into the system. To minimize problems due to noise radiating directly onto the PC board from nearby high frequency circuitry, all components associated with the MC33121 should be physically as close as possible to the IC. The most sensitive pins in this respect are the CP, CN, RSI, TSI, VAG and RXI pins. Keeping the tracks short minimizes their "antenna" effect. c) Transient Conditions When transient voltages come in to Tip and Ring, the transient currents, which can be several amperes, must be carried by the ground line (VCC) an/or the VEE line. These tracks, along with the protection and clamping devices, must be designed for these currents at the frequencies involved. If the tracks are narrow, not only may they be destroyed by the high currents, but their inductance can allow the voltage at the IC, and other nearby components, to rise to damaging levels. The protection circuits shown in Figure 4, and in other figures in this data sheet, are such that the bulk of the transient energy is dissipated by external components (the protection resistors and the clamp diodes). The MC33121 has internal diodes to limit voltage excursions on the pins, and to pass a small amount of the transient current -- typically less than 1.0 A peak. The arrangement of the diodes is shown in Figure 40. d) Interconnection of the four-wire side The connections on the four-wire side to the codec and other digital circuitry involves keeping digital noise out of the speech paths, and also ensuring that potentially destructive transients on Tip and Ring do not get through to the + 5.0 V system.
VDD
+ 5.0 V
MC33121
ST1
ST2 CP VDG TSI RSI 14 V TO DIGITAL GROUND
VAG TO ANALOG GROUND RXI TXO
CN RFO BN EN All zener diodes are 7.0 V, except where noted. VEE 14 V 9.0 V CF VQB
Figure 40. Protection Diodes
MC33121 24
MOTOROLA
Basically, digital connections to ST1 and ST2 should be referenced to the VDD and VDG pins, while the transmit and receive analog signals should be referenced to the analog ground (VAG). VCC should be connected to a clean battery ground, and generally should not be connected directly to VDG and/or VAG (on the line card) when strong transients are anticipated. Even with a good layout, VCC can move several volts when a transient hits, possibly damaging components on the + 5.0 V line if their grounds have a direct connection at the line card. The MC33121 is designed to allow VCC to move as much as 30 V with respect to VDG and VAG on a transient basis only. VCC and the other grounds should preferably be connected together at the power supply rather than at the IC. Internally, the MC33121 has clamp diodes on the 4-wire side pins as indicated in Figure 40. If the codec has a single ground pin, as in Figure 41, it will be the reference for both the digital and analog signals, and must be connected to both VAG and VDG on the MC33121. If the codec has separate digital and analog grounds, as in Figure 42 (the MC145503 internally generates the analog ground), then each ground should be connected to the
appropriate ground on the MC33121. e) Other A 0.1 F capacitor should be provided across VCC to VEE on the MC33121 to help keep idle channel noise to a minimum. The CQB capacitor (on the VQB pin) forms a pole with an internal 7.5 k resistor to filter noise from the VEE pin, providing an internal quiet battery supply for the speech amplifiers. Power supply rejection will depend on the value and quality of this capacitor at the frequencies of concern. Tantalum capacitors generally have better high frequency characteristics then electrolytics. See Figure 17 and 18 for ripple rejection characteristics (the four-wire data was measured at pin 11 (TXO)). Figure 16 indicates ripple rejection from the + 5.0 V supply (VDD). In general, pc board tracks carrying analog signals (on the four-wire side and Tip/Ring) should not be routed through the digital section where they could pick up digital noise. Any tracks longer than a few inches should be considered an antenna and should be checked for potential noise or RFI pickup which could affect the circuit operation.
BATTERY GROUND DIGITAL GROUND + 5.0 V 0.1 - 5.0 V
VCC
VDD 0.1 VDG VAG RXI 5 F 0.1
VCC GNDA
VBB
VFRO VFXI+ VFXI- GSX
- + + - MC145554
MC33121 TXO 10 F VQB 0.1 VEE
DIGITAL INTERFACE
BATTERY SUPPLY
Figure 41. Connection to a CODEC With a Single Ground
BATTERY GROUND DIGITAL GROUND + 5.0 V 0.1 - 5.0 V
VCC
VDD 0.1 VDG VAG 5 F 0.1
VCC VLS VAG - + + - MC145503
VSS
MC33121 RXI RXO +TX TXO 10 F VQB VEE -TX TXI DIGITAL INTERFACE
BATTERY SUPPLY 0.1
Figure 42. Connection to a CODEC With Separate Grounds
MOTOROLA
MC33121 25
Alternate Circuit Configurations a) Loop Current Limit Replacing the RRF resistor with the circuit in Figure 43 will change the DC loop current characteristics in two ways from the graphs of Figures 5 - 7; a) the maximum loop current on a short line can be reduced while increasing the current on a long line, and b) the temperature dependence of the maximum current is reduced to the TC of the external reference diode.
VAG RXI RRF1 LM385-1.2
a small amount ([ 10%) flows through the sense resistors and the CP, CN, RSI pins. On a positive transient, all the current is directed to ground. The diode in the NPN's collector prevents reverse current through the base-collector junction of the transistor during a negative transient.
50
IL, LOOP CURRENT (mA)
40
30
RRF2 RFO
20 RS = 9.1 k VEE = - 24 V TA = 25C 0 200 RRF1 = 4.3 k RRF2 = 820 400 RL, LOOP RESISTANCE () 600 800
Figure 43. Alternate Current Limit Circuit The LM385-1.2 is a precision temperature stable zener diode. As the load impedance at Tip and Ring is reduced, the voltage at RFO goes increasingly negative. When the zener diode is turned on, the current into RXI is then clamped at a value determined by RRF1 and the zener diode. To calculate the two resistors, use the following procedure: RRF1 must be > 0.7 * (RRF1 + RRF2); Determine RRF1 to set the current limit on a short line by using the following equation: RRF1
10
Figure 44. Loop Current versus Loop Resistance Alternate Loop Current Limit Configuration
VCC EP BP 1.5KE15 0.01 100 V RP TIP RING RP 1.5KE30 0.01 100 V 1N4002 BN EN - 24 V VEE 14 V 1.0 k CN 9100 TSI RSI 9100 14 V 1.0 k CP MC33121
+I
102 * 1.23 V - 3.0 mA L(max)
(23)
Then using Equation 1 calculate RRF for the long line current. RRF2 is then determined by; RRF2 = RRF - RRF1 (24)
Figure 44 illustrates one example using the above circuit. Comparing this graph to the 5100 curve of Figure 7 shows a substantial decrease in the current limit (at RL = 0), resulting in reduced power consumption and dissipation. Use of this circuit does not affect the hookswitch or fault thresholds. b) Protection Scheme The protection circuit shown in Figure 45 has the advantage of drawing of the transient current from ground (VCC) on a negative transient, rather than from the VEE line as the circuit of Figure 4 does. The majority of the transient current flows through the RP resistors and the Mosorbs while
[90%
All zener diodes are 7.0 V except as noted.
Figure 45. Alternate Protection Scheme
MC33121 26
MOTOROLA
CIRCUIT PERFORMANCE
The following three circuits are presented as typical application examples, and the accompanying graphs indicate their measured performance. The first circuit (Figure 46) has a 600 pure resistance as the AC load. The second circuit (Figures 47) has as an AC load a 900 resistor in series with a 2.16 F capacitor. The third circuit (Figure 48) has as an
20 19 MJD253 0.01 1.0 k, 2% 100 TIP RAC 600 VL RING VEE 9.1 k 9.1 k 1.0 k, 2% 0.01 100 MJD243 VEE 17 16 5 4 3 2 1 - 28 V 0.1 18
AC load, a complex network composed of an 820 resistor in parallel with 0.115 F, and those in series with a 220 resistor. In the graphs of Figures 49 - 51, RL = Return Loss, THR = Transhybrid Rejection, GTX = Transmit Gain, GRX = Receive Gain.
VCC EP BP CP TSI MC33121 RSI CN BN EN VEE
VDD PDI ST1 VDG VAG RXI RFO TXO CF VQB
15 12 13 14 9 10 8 11 7 6 300 4.7 k 1.0 F 0.1
+ 5.0 V ST2/PDI 5.0 F ST1
30.6 k 20.3 k 600 15.8 k 10 k 1.0 F 20 10 F 0.005 600 1.0 F 31.6 k - +
RECEIVE IN (VRX)
TRANSMIT OUT (VTX)
Figure 46. 600 System
20 19 MJD253 0.01 1.0 k, 2% 100 TIP VEE RAC 900 2.16 F VL RING 9.1 k 9.1 k 1.0 k, 2% 0.01 100 MJD243 VEE 17 16 5 4 3 2 1 - 28 V 0.1 18
VCC EP BP CP TSI MC33121 RSI CN BN EN VEE
VDD PDI ST1 VDG VAG RXI RFO TXO CF VQB
15 12 13 14 9 10 8 11 4.7 k 62 nF 0.1
+ 5.0 V ST2/PDI 5.0 F ST1
45.9 k 42 nF 31.2 k 31.6 k 31.6 k 10 k 1.0 F 1.0 F - +
RECEIVE IN (VRX)
7 6
300 20 10 F
TRANSMIT OUT (VTX)
Figure 47. 900 and 2.16 F System
MOTOROLA
MC33121 27
20 19 MJD253 18 0.01 RAC 820 VL RING 220 1.0 k, 2% 0.01 100 4 9.1 k 5 100 1.0 k, 2% 17 9.1 k 16
VCC EP BP CP TSI MC33121 RSI CN
VDD PDI ST1 VDG VAG RXI
15 12 13 14 9 10 4.7 k 0.1
+ 5.0 V ST2/PDI 5.0 F ST1
VEE TIP
2.25 nF 41.8 k 7.61 k 28.4 k 31.6 k 10 k 1.0 F 1.0 F - + TRANSMIT OUT (VTX) 11.2 k 31.6 k
RECEIVE IN (VRX)
RFO
8 3.3 nF
MJD243 3 BN VEE 2 1 - 28 V 0.1 EN VEE
TXO 11 CF VQB 7 6
1.0 F 300 20 10 F
Figure 48. 220 and 820 //0.115 F System
90 RL 70 TEST RESULTS (dB) TEST RESULTS (dB) 50 30 +0.1 GTX 0 GRX -0.1 100 1.0 k f, FREQUENCY (Hz) 10 k
50 RL 40 30 20 +0.2 GTX 0 GRX -0.2 100 1.0 k f, FREQUENCY (Hz) 10 k THR
THR
Figure 49. Circuit Performance, 600 System
Figure 50. Circuit Performance 900 and 2.16 F System
MC33121 28
MOTOROLA
80 60 TEST RESULTS (dB) 40 THR 20 +0.2 0 -0.2 100 RL VA REFERENCE NETWORK IL R Reference Network = RAC of Figures 46 to 48. VB Return Loss = 20 log VA VA - VB T MC33121 CIRCUIT (FIGURES 46, 47 OR 48)
VB GTX GRX
1.0 k f, FREQUENCY (Hz)
10 k
)
Figure 51. Circuit Performance 820 //0.115 F and 220 System
Figure 52. Return Loss Test Circuit for Figures 46 to 51
GLOSSARY
ATTENUATION -- A decrease in magnitude of a communication signal, usually expressed in dB. BALANCE NETWORK -- That part of the SLIC circuit which provides transhybrid rejection. BANDWIDTH -- The range of information carrying frequencies of a communication system. BATTERY -- The voltage which provides the loop current, and in some cases powers the SLIC circuit. The name derives from the fact that COs have always used batteries, in conjunction with AC power, to provide this voltage. BATTERY FEED RESISTANCE -- The equivalent Thevenin DC resistance of the SLIC circuit for supplying loop current. Traditionally it is 400 . C-MESSAGE FILTER -- A frequency weighting which evaluates the effects of noise on a typical subscriber's system. CENTRAL OFFICE -- Abbreviated CO, it is a main telephone office, usually within a few miles of its subscribers, that houses switching gear for interconnection within its exchange area, and to the rest of the telephone system. A typical CO can handle up to 10,000 subscriber numbers. CODEC -- Coder/Decoder -- Interfacing between the SLIC and the digital switch, it converts the SLIC's transmit signal to digital, and converts the digital receive signal to analog. dB -- A power or voltage measurement unit, referred to another power or voltage. It is generally computed as: 10 * log (P1/P2) for power measurements, and 20 * log (V1/V2) for voltage measurements. dBm -- An indication of signal power. 1.0 mW across 600 , or 0.775 Vrms, is defined as 0 dBm. Any other voltage level is converted to dBm by: dBm = 20 * log (Vrms/0.775), or dBm = [20 * log (Vrms)] + 2.22. dBmp -- Indicates dBm measurement using a psophometric weighting filter. dBrn -- Indicates a dBm measurement relative to 1.0 pW power level into 600 . Generally used for noise measurements, 0 dBrn = - 90 dBm. dBrnC -- Indicates a dBrn measurement using a C- message weighting filter. DTMF -- Dual Tone Multifrequency. It is the "tone dialing" system based on outputting two non-harmonic related frequencies simultaneously to identify the number dialed. Eight frequencies have been assigned to the four rows and four columns of a keypad. FAULT -- An incorrect condition where Tip is accidentally connected to the battery voltage, or Ring is connected to ground, or both. The most common fault is Ring to ground. FOUR WIRE CIRCUIT -- The portion of a telephone, or central office, which operates on two pairs of wires. One pair is for the transmit path, and one pair is for the receive path. FULL DUPLEX -- A transmission system which permits communication in both directions simultaneously. The standard handset telephone system is full duplex. GAIN -- The change in signal amplitude (increase or decrease) after passing through an amplifier, or other circuit stage. Usually expressed in dB, an increase is a positive number, and a decrease is a negative number.
MOTOROLA
MC33121 29
HALF DUPLEX -- A transmission system which permits communication in one direction at a time. CB radios, with "push-to-talk" switches, and voice activated speakerphones, are half duplex. HOOKSWITCH -- A switch, within the telephone, which connects the telephone circuit to the subscriber loop. The name derives from old telephones where the switch was activated by lifting the receiver off and onto a hook on the side of the phone. HYBRID -- Another name for a two-to-four wire converter. IDLE CHANNEL NOISE -- Residual background noise when transmit and receive signals are absent. LINE CARD -- The PC board and circuitry in the CO or PBX which connects to the subscriber's phone line. A line card may hold circuitry for one subscriber, or a number of subscribers. LONGITUDINAL BALANCE -- The ability of the SLIC to reject longitudinal signals on Tip and Ring. LONGITUDINAL SIGNALS -- Common mode signals. LOOP -- The loop formed by the two subscriber wires (Tip and Ring) connected to the telephone at one end, and the central office (or PBX) at the other end. Generally, it is a floating system not referred to ground, or AC power. LOOP CURRENT -- The DC current which flows through the subscriber loop. It is typically provided by the central office or PBX, and ranges from 20 to 120 mA. OFF-HOOK -- The condition when the telephone is connected to the phone system, permitting the loop current to flow. The central office detects the DC current as an indication that the phone is busy. ON-HOOK -- The condition when the telephone is disconnected from the phone system, and no DC loop current flows. The central office regards an on-hook phone as available for ringing. PABX -- Private Automatic Branch Exchange. In effect, a miniature central office, it is a customer owned switching system servicing the phones within a facility, such as an office building. A portion of the PABX connects to the Bell (or other local) telephone system. PROTECTION, PRIMARY -- Usually consisting of carbon blocks or gas discharge tubes, it absorbs the bulk of a lightning induced transient by clamping the voltages to less than 1500 V. PROTECTION, SECONDARY -- Usually located on the line card, it protects the SLIC and associated circuits from transient surges. Typically, it must be capable of clamping a 1.5 kV surge of 1.0 ms duration. PULSE DIALING -- A dialing system whereby the loop current is interrupted a number of times in quick succession. The number of interruptions corresponds to the number dialed, and the interruption rate is typically 10 per second. The old rotary phones, and many new pushbutton phones, use pulse dialing.
RECEIVE PATH -- Within the CO or PBX it is the speech path from the internal switching system towards the phone line (Tip & Ring). REN -- Ringer Equivalence Number. An indication of the impedance or loading factor of a telephone bell or ringer circuit. An REN of 1.0 equals k . The Bell system typically permits a maximum of 5.0 REN (1.6 k) on an individual subscriber line. A minimum REN of 0.2 (40 k) is required by the Bell system.
[8.0
RETURN LOSS -- Expressed in dB, it is a measure of how well the SLIC's AC impedance matches the line's AC characteristic impedance. With a perfect match, there is no reflected signal, and therefore infinite return loss. It is calculated from: RL
+ 20 * log (ZLine ) ZCKT)) (Z -Z
Line CKT
RING -- One of the two wires connecting the central office to a telephone. The name derives from the ring portion of the plugs used by operators (in older equipment) to make the connection. Ring is traditionally negative with respect to Tip. SLIC -- Subscriber Line Interface Circuit. It is the circuitry within the CO or PBX which connects to the user's phone line. SUBSCRIBER -- The customer at the telephone end of the line. SUBSCRIBER LINE -- The system consisting of the user's telephone, the interconnecting wires, and the central office equipment dedicated to that subscriber (also referred to as a loop). TIP -- One of the two wires connecting the central office to a telephone. The name derives from the tip of the plugs used by operators (in older equipment) to make the connection. Tip is traditionally positive with respect to Ring. TRANSHYBRID REJECTION -- The rejection (in dB) of the reflected signal in the transmit path resulting from a receive signal applied to the SLIC. TRANSMIT PATH -- Within the CO or PBX it is the speech path from the phone line (Tip & Ring) towards the internal switching system. TWO WIRE CIRCUIT -- Refers to the two wires connecting the central office to the subscriber's telephone. Commonly referred to as Tip and Ring, the two wires carry both transmit and receive signals in a differential manner. TWO-TO-FOUR WIRE CONVERTER -- A circuit which has four wires (on one side) -- two (signal & ground) for the outgoing signal, and two for the incoming signal. The outgoing signal is sent out differentially on the two wire side (the other side), and incoming differential signals received on the two wire side are directed to the four wire side. Additional circuit within cancels the reflected outgoing signal to keep it separate from the incoming signal. VOICEBAND -- That portion of the audio frequency range used for transmission across the telephone system. Typically, it is 300 to 3400 Hz.
MC33121 30
MOTOROLA
PACKAGE DIMENSIONS
P SUFFIX PLASTIC PACKAGE CASE 738-03 -A-
20 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
B
1 10
C
L
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
DIM A B C D E F G J K L M N
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MOTOROLA
MC33121 31
FN SUFFIX PLCC CASE 776-02 B -N- Y BRK U D Z -L- -M- 0.007 (0.180)
M
0.007 (0.180)
M
T L-M
S
N
S S
T L-M
N
S
W
28 1
D
X VIEW D-D
G1
0.010 (0.250)
S
T L-M
S
N
S
V
A Z R C
0.007 (0.180) 0.007 (0.180)
M M
T L-M T L-M
S S
N N
S S
H
0.007 (0.180)
M
T L-M
S
N
S
E 0.004 (0.100) G G1 0.010 (0.250)
S
K1
J
-T- VIEW S
SEATING PLANE
K F VIEW S 0.007 (0.180)
M
T L-M
S
N
S
T L-M
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10_ 0.410 0.430 0.040 ---
MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10_ 10.42 10.92 1.02 ---
How to reach us: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com
JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MC33121 32
*MC33121/D*
MC33121/D MOTOROLA

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